1. Field of the Invention
The present invention relates to a plasma display panel (PDP) driving apparatus, and more particularly, to a PDP driving apparatus for applying a voltage to electrodes of the PDP.
2. Discussion of the Background
FIG. 1 shows a conventional three-electrode surface discharge PDP.
Referring to FIG. 1, the conventional surface discharge PDP 1 includes front and rear glass substrates 100 and 106. Address electrode lines A1, . . . , Am, front and rear dielectric layers 102 and 110, scan electrode lines Y1, . . . , Yn, sustain electrode lines X1, . . . , Xn, a fluorescent layer 112, barrier ribs 114, and a protective layer 104 are arranged between the front and rear glass substrates 100 and 106. The protective layer 104 may be made of, for example, magnesium oxide (MgO).
The address electrode lines A1, . . . , Am are arranged on an upper surface of the rear glass substrate 106 in a predetermined pattern, and the rear dielectric layer 110 covers the address electrode lines A1, . . . , Am. The barrier ribs 114, which define discharge cells, are arranged on an upper surface of the rear dielectric layer 110 and are substantially parallel to the address electrode lines A1, . . . , Am. The barrier ribs 114 prevent optical crosstalk between discharge cells. The fluorescent layer 112 is arranged on sides of the barrier ribs 114 and the upper surface of the rear dielectric layer 110 not covered by the barrier ribs 114.
The sustain electrode lines X1, . . . , Xn and the scan electrode lines Y1, . . . , Yn are arranged on a lower surface of the front glass substrate 100 in a predetermined pattern to cross the address electrode lines A1, . . . , Am. Discharge cells are provided to correspond to the crossing points. The sustain electrode lines X1, . . . , Xn and the scan electrode lines Y1, . . . , Yn may include transparent electrode lines Xna, . . . , Yna and metallic electrode lines Xnb, . . . , Ynb, respectively. The transparent electrode lines Xna, . . . , Yna may be made of a conductive transparent material such as indium tin oxide (ITO). The metallic electrode lines Xnb, . . . , Ynb increase the conductivity of the sustain electrode lines. The front dielectric layer 102 covers the sustain electrode lines X1, . . . , Xn and the scan electrode lines Y1, . . . , Yn. The protective layer 104, which protects the PDP 1 from a strong electric field, covers the front dielectric layer 102. A discharge space 108 is filled with a plasma-forming discharge gas.
Generally, driving operations of the PDP 1 are divided into reset, address, and sustain discharge periods PR, PA, and PS, which are sequentially performed in individual subfields. In the reset period PR, all discharge cells are provided with a substantially uniform charge state. In the address period PA, the discharge cells to be turned on are selected. In the sustain discharge period PS, sustain discharge is performed in the selected discharge cells, thereby generating plasma from the plasma-forming discharge gas. In turn, ultraviolet (UV) light emitted from the plasma excites the fluorescent layer coated in the discharge cells, and the fluorescent layer emits light as it transitions from an excited state to a ground state. The emitted light forms images displayed by the PDP.
FIG. 2 shows a conventional PDP driving apparatus for the PDP of FIG. 1.
Referring to FIG. 2, the PDP driving apparatus includes an image processor 200, a logic controller 202, an address driver 206, an X driver 208, and a Y driver 204. The image processor 200 outputs image signals (i.e. internal image signals) after processing an input image signal. For example, the internal image signals may include 8-bit R, G, B image data, a clock signal, a horizontal synchronization signal, and a vertical synchronization signal. The logic controller 202 generates driving control signals including an address signal SA, a Y driving control signal SY, and an X driving control signal SX. The address driver 206 generates a display data signal by processing the address signal SA and applies the display data signal to the address electrode lines A1, . . . , Am. The X driver 208 processes the X driving control signal SX and applies the processed X driving control signal SX to the sustain electrode lines X1, . . . , Xn. The Y driver 204 processes the Y driving control signal SY and applies the processed Y driving control signal SY to the scan electrode lines Y1, . . . , Yn.
FIG. 3 shows an address display separation (ADS) driving scheme for the scan electrode lines in the PDP of FIG. 1.
In order to perform time-division gray display, a unit frame may be divided into a predetermined number of subfields, typically, 8 subfields SF1, . . . , and SF8. Each subfield SF1, . . . , and SF8 may be divided into a reset period (not shown), an address period A1 . . . , A8, and a sustain discharge period S1 . . . , S8.
In the address period A1 . . . , A8, display data signals are applied to the address electrode lines A1, . . . , Am, and scan pulses are sequentially applied to the scan electrode lines Y1, . . . , Yn, to generate wall charges in selected discharge cells.
In the sustain discharge period S1, . . . , S8, sustain pulses are alternately applied to the scan electrode lines Y1, . . . , Yn and the sustain electrode lines X1, . . . , Xn to generate a sustain discharge in the selected discharge cells.
PDP's brightness is proportional to the number of sustain discharge pulses in the sustain discharge periods S1, . . . , and S8 of one unit frame. In a case where one image is represented in 256 gray scales by using one frame having 8 subfields, sustain pulses having different ratios of 1, 2, 4, 8, 16, 32, 64, and 128 may be allocated to the 8 subfields SF1, . . . , and SF8, respectively. Hence, for example, a brightness of a 133 gray scale may be obtained by addressing and sustain-discharging a discharge cell in the first, third, and eighth subfields SF1, SF3, and SF8.
The number of sustain discharge pulses allocated to each subfield may be determined according to weighting factors for the subfields in an automatic power control (APC) stage. Additionally, the number of the sustain discharge pulses allocated to the subfields may be determined according to gamma characteristics or panel characteristics. For example, the gray scale allocated to the fourth subfield SF4 may be decreased from 8 to 6, and the gray scale allocated to the sixth subfield SF6 may be increased from 32 to 34. Further, the number of subfields in one frame may be determined according to a design specification.
FIG. 4 shows a timing diagram of driving signals that may be used to drive the PDP of FIG. 1. Referring to FIG. 4, the driving signals are applied to the address electrode lines A1, . . . , Am, the sustain electrode lines X1, . . . , Xn, and the scan electrode lines Y1, . . . , Yn, and a subfield SF may include a reset period PR, an address period PA, and a sustain discharge period PS.
In the reset period PR, a reset pulse is applied to the scan electrode lines Y1, . . . , Yn to initialize wall charge states of all discharge cells. The reset pulse may include a rising ramp followed by a falling ramp. Applying the rising ramp to the scan electrode lines Y1, . . . , Yn increases the voltage of each scan electrode line Y1, . . . , Yn from the sustain discharge voltage Vs to a highest rising voltage Vset+Vs. Applying the falling ramp to the scan electrode lines Y1, . . . , Yn decreases the voltage each scan electrode line Y1, . . . , Yn from the sustain discharge voltage Vs to a lowest falling voltage Vnf. When applying the falling ramp, a bias voltage Ve is applied to the sustain electrode lines X1, . . . , Xn, and a ground voltage Vg is applied to the address electrode lines A1, . . . , Am. As FIG. 4 shows, the bias voltage Ve may be higher than the sustain discharge voltage Vs.
In the address period PA, in order to select discharge cells to be turned on, scan pulses having a voltage Vscl are sequentially applied to the scan electrode lines Y1, . . . , Yn. Here, unselected scan electrode lines are biased at a high scan voltage Vsch. A display data signal having an address voltage Va is simultaneously applied to the address electrode lines A1, . . . , Am to select the corresponding discharge cells. The sustain electrode lines X1, . . . , Xn are biased at the bias voltage Ve during the address period PA.
In the sustain discharge period PS, in order to sustain-discharge the discharge cells selected in the address period PA, a sustain pulse having a sustain discharge voltage Vs is alternately applied to the scan electrode lines Y1, . . . , Yn and the sustain electrode lines X1, . . . , Xn.
FIG. 5 shows an example of the X driver in the PDP driving apparatus of FIG. 2.
Referring to FIG. 5, the X driver 208 includes a first voltage switching unit 55, a second voltage switching unit 57, a main switching unit 59, and an energy recovery circuit 53. The first voltage switching unit 55 applies a sustain pulse having a sustain discharge voltage Vs and a ground voltage Vg to the sustain electrode lines X1, . . . , Xn, and the second voltage switching unit 57 applies a bias voltage Ve to the sustain electrode lines X1, . . . , Xn. The main switching unit 59 separates application of the bias voltage Ve from application of the sustain discharge voltage Vs and the ground voltage Vg, and the energy recovery circuit 53 collects charges in the discharge cells or emits collected charges into the discharge cells.
Hereinafter, the PDP is referred to as a panel capacitor. Additionally, the panel capacitor may denote a discharge cell.
The energy recovery circuit 53 includes an inductor L1, an over-voltage clamping preventing unit 52, an energy recovery switching unit 51, and an energy storage unit 54. The inductor L1 has one terminal coupled with the main switching unit 59. The over-voltage clamping preventing unit 52 has two diodes D2 and D3 coupled with the connection node N1 (the other terminal of the inductor L1) to maintain the connection node N1 within a voltage range from the sustain discharge voltage Vs to the ground voltage Vg. The energy recovery switching unit 51 has two diodes D4 and D5 coupled with the connection node N1, and two switching elements S5 and S6 coupled with the diodes D4 and D5, respectively, to collect the charges in the panel capacitor Cp or apply collected charges to the panel capacitor Cp. The energy storage unit 54 stores the collected charges and emits the stored charges to the panel capacitor Cp.
If the bias voltage Ve exceeds the sustain discharge voltage Vs as shown in FIG. 4, the X driver 208 prevents a current from flowing from the second voltage switching unit 57 to the first voltage switching unit 55 by turning the main switching unit 59 on and off. Since a large current flows in the main switching unit 59, the main switching unit 59 must have a sufficiently large current capacity. Conventionally, the main switching unit 59 is typically constructed with a plurality of serially-connected large-current-capacity elements. However, this construction of the main switching unit 59 increases the production cost of the PDP driving apparatus. Therefore, there is a need to improve the PDP driving apparatus.
FIG. 6 shows another example of the X driver for the PDP driving apparatus of FIG. 2. FIG. 7 is a waveform diagram of a sustain pulse applied to the sustain electrode lines in a sustain discharge period PS by the X driver of FIG. 6.
The X driver 208 of FIG. 6 has a similar construction to that of the X driver of FIG. 5. The X driver 208 of FIG. 6 includes a first voltage switching unit 155, a second voltage switching unit 157, and an energy recovery circuit 153. The first voltage switching unit 155 applies a sustain pulse having the sustain discharge voltage Vs and the ground voltage Vg to the panel capacitor Cp, and the second voltage switching unit 157 applies the bias voltage Ve to the panel capacitor Cp. The energy recovery circuit 153 collects charges in the discharge cells or emits collected charges into the discharge cells. The energy recovery circuit 153 is similar to the energy recovery circuit 53 of FIG. 5. However, instead of the main switching unit 59 of FIG. 5, the X driver 208 of FIG. 6 has an additional first diode D11 coupled with the first voltage source Vs in order to prevent influence of the bias voltage Ve (from the second switching unit 157) on the first voltage switching unit 155. Additionally, in an over-voltage clamping preventing unit 152, the cathode of the second diode D12 is coupled with the second voltage source Ve. Therefore, the production cost of the PDP driving apparatus may be reduced. Additionally, the influence of the bias voltage Ve on the first voltage switching unit 155 may be minimized. However, the over-voltage clamping preventing unit 152 has a clamping range (that is, a clamping performance) from the bias voltage Ve to the ground voltage Vg, instead of from the sustain discharge voltage Vs to the ground voltage Vg. According to this change in clamping performance, as FIG. 7 shows, the sustain pulse applied to the sustain electrode lines X1, . . . , Xn in the sustain discharge period PS may increase up to the bias voltage Ve, so that overshoot occurs. The overshoot negatively affects the PDP's performance since it causes unstable light emission in the sustain discharge period PS.